Manipulating matter at the nanometer scale is important for many electronic, chemical and biological advances (See Li et al., “Ion beam sculpting at nanometer length scales”, Nature, 412: 166–169, 2001). Such techniques as “ion beam sculpting have shown promise in fabricating molecule scale holes and nanopores in thin insulating membranes. These pores have also been effective in localizing molecular-scale electrical junctions and switches (See Li et al., “Ion beam sculpting at nanometer length scales”, Nature, 412: 166–169, 2001).
Artificial nanopores have been fabricated by a variety of research groups with a number of materials. Generally, the approach is to fabricate these nanopores in a solid-state material or a thin freestanding diaphragm of material supported on a frame of thick silicon to form a nanopore chip. Some materials that have been used to date for the diaphragm material include silicon nitride and silicon dioxide.
A problem with artificial nanopores fabricated on a silicon frame is that silicon is a semiconductor and has low resistivity, typically in the range of 1–50 Ohm-cm, which is much lower than the resistivity of a true insulator such as silicon nitride or silicon dioxide. For example, silicon nitride typically has a resistance greater than 1010 Ohm-cm while even high-resistivity silicon has a resistivity on the order of only 104 Ohm-cm. Thus the silicon substrate can be considered to be a near short circuit for the purposes of capacitance calculation, and the resulting artificial nanopore on a silicon substrate, and any electrical leads associated with the nanopore, have undesirably high capacitance values. For example, if the silicon nitride layer is 200 nm thick and the contact area between the nanopore chip and a conductive liquid is a circle 1 mm in diameter, the capacitance across the insulator can approach 260 picoFarads (260 pF), which severely limits the frequency bandwidth for which electrical current through the nanopore can be measured.
This problem of high capacitance may be reduced, for a simple nanopore structure, by building an associated external package which limits the contact area between a conductive liquid and the nanopore substrate, so that total capacitance across the insulator is reduced to a value on the order of 1 picoFarad (1 pF). But using external packaging alone to produce a small liquid contact area is often difficult and problematic, and that approach ignores the need to place low-capacitance electrical leads on the surface of the insulator layer over the silicon frame. Therefore, an approach is needed which provides low capacitance for a relatively large liquid contact area to the insulator, and at the same time provides low capacitance for electrical leads running along the surface of the insulator.
These and other problems with the prior art processes and designs are obviated by the present invention. The references cited in this application infra and supra, are hereby incorporated in this application by reference. However, cited references or art are not admitted to be prior art to this application.